1. Field of the Invention
The present invention relates to integrated circuits. More particularly, the present invention relates to bipolar transistor devices and methods for the fabrication thereof.
2. Description of Related Art
Due to their fast switching times and high current densities, field effect transistor (FET) devices are generally preferred as semiconductor device architecture in today's technology. Despite the prevalence of FETs, however, bipolar transistors have superior device attributes in some areas, especially for analogue and power gain applications. For example, bipolar transistor devices have higher speed, higher current density, lower noise and higher cutoff frequency than conventional FET devices. A typical drawback of bipolar devices, having high static power dissipation, becomes less relevant when circuits of FET devices increase their operating speed. When that happens, FET devices also create high static power dissipation.
Conventional bipolar devices, however, require: (1) abrupt emitter to base junctions and; (2) well controlled base region lengths. Because of these requirements, conventional bipolar devices are typically not scaled for density.
To reduce the size of semiconductor devices, it has been known that vertical bipolar transistors have been utilized, especially when the bipolar transistors are integrated with FET devices in a single chip. It has been further known that finned bipolar transistors, which incorporate fin forming techniques previously used to form fin bipolar transistor devices, have been used for semiconductor devices. This architecture allows scaled finned bipolar devices to be formed on a single chip substrate.
As feature sizes of the devices get increasingly smaller (commensurate with current technology), however, accurately and consistently contacting the collector and emitter regions with the contact line becomes a major problem. In some instances, collector and emitter regions are used to contact the fins instead in order to provide mechanical stability during processing, which simplifies the device contacting scheme and reduces external resistance. However, the regions still need to be precisely aligned with the contact line in order to achieve a practical contact line pitch (in the case of logic layouts using minimum contact line pitch) and to minimize variations in extrinsic resistance and parasitic capacitance. Thus, properly and consistently aligning the collector and emitter regions with the contact line is difficult.
Accordingly, bipolar transistor devices and methods for fabrication thereof that improve the device contacting scheme and scalability of the devices can be desirable.